Power-Efficient Microcontrollers (MCUs) with Advanced Peripherals Based on Arm® Cortex®-M4 Core

LPC540XX

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Offering flashless design and security integration, the LPC540xx family of MCUs combines a 180 MHz Arm® Cortex®-M4 core with a power-efficient and unique architecture, advanced HMI and flexible communication peripherals for real-time performance in the next-generation IoT. Featuring flexibility with a quad SPI flash interface, CAN, graphic LCD and up to 11 channels for FlexComm, the LPC540xx family provides the ability to adapt as requirements change. Compatibility within the LPC54000 series enables the LPC540xx MCU family to provide a seamless migration path for increasing processing power and adding the flexibility of additionally advanced peripherals.

For added security, the new LPC54S0xx MCU devices in this family provide Physical Unclonable Function (PUF) root key using dedicated SRAM for silicon fingerprint making it possible to generate, store, and reconstruct keys. In addition, the LPC54S0xx devices feature an on-chip hardware AES engine to protect the image content and accelerate processing for data integrity and proof of origin. Data can be encrypted or decrypted by the AES engine using the encrypted key stored in the OTP, SRAM PUF-based or a software supplied key.

This device is fully supported by NXP’s MCUXpresso Software and Tools, a comprehensive and cohesive set of free software development tools for Kinetis, LPC and i.MX RT microcontrollers. MCUXpresso SDK also includes project files for Keil MDK and IAR EWARM.

Product Details

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Block Diagram

LPC540xx MCU

LPC540xx MCU Family Block Diagram
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Features

Arm Cortex-M4 core

  • Arm Cortex-M4 processor, running at a frequency of up to 180 MHz.
  • Floating Point Unit (FPU) and Memory Protection Unit (MPU).
  • Arm Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
  • Non-maskable Interrupt (NMI) input with a selection of sources.
  • Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators, and four watchpoints. Includes Serial Wire Output and ETM Trace for enhanced debug capabilities, and a debug timestamp counter.
  • System tick timer.

On-chip memory

  • 360 KB total SRAM consisting of 160 KB contiguous main SRAM and an additional 192 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB traffic.
  • General-purpose One-Time Programmable (OTP) memory for *AES keys and user application specific data.
  • Up to 4 MB On-chip Flash**

ROM API support

  • In-Application Programming (IAP) and In-System Programming (ISP).
  • ROM-based USB drivers (HID, CDC, MSC, and DFU).
  • Booting from USART, SPI, I2C, USB0/1, EMC (static memory), and SPIFI (QSPI flash).
  • OTP API for programming OTP memory.
  • Random Number Generator (RNG) API.*
  • AES API for programming AES memory.*
  • RSA API calls.*
  • Secure boot using RSA and SHA256 with public key signing (image authentication boot).*
  • Secure boot using AES128 in GCM mode to authenticate and decrypt firmware (Encrypted image boot).

Serial interfaces

  • Flexcomm Interface contains up to 11 serial peripherals. Each Flexcomm Interface (except flexcomm 10, which is dedicated for SPI) can be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud-rate generator.
  • I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to 1Mbit/s and with multiple address recognition and monitor mode. Two sets of true I2C pads also support High-Speed Mode (3.4 Mbit/s) as a target.
  • Two ISO 7816 Smart Card Interfaces with DMA support.
  • USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
  • USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode.
  • SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI flash memory at a much higher rate than standard SPI or SSP interfaces.
  • Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and dedicated DMA controller.
  • Two CAN FD modules with dedicated DMA controller.

Digital peripherals

  • DMA controller with 32 channels and up to 24 programmable triggers, able to access all memories and DMA-capable peripherals.
  • LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film Transistor (TFT) displays. It has a dedicated DMA controller, selectable display resolution (up to 1024 x 768 pixels), and support up to 24-bit true-color mode.
  • External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, in addition to dynamic memories such as single data rate SDRAM with an SDRAM clock of up to 100 MHz. EMC bus width (bit) on LQFP100 and TFBGA100 packages support up to 8/16 data line wide static memory.
  • Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
  • CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support.
  • Up to 171 General-Purpose Input/Output (GPIO) pins.
  • GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports.
  • Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising, falling or both input edges.
  • Two GPIO Grouped Interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states.
  • CRC engine.

Analog peripherals

  • 12-bit ADC with 12 input channels and with multiple internal and external trigger inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two independent conversion sequences.
  • Integrated temperature sensor connected to the ADC.

Timers

  • Five 32-bit general purpose timers/counters, four of which support up to four capture inputs and four compare outputs, PWM mode, and external count input. Specific timer events can be selected to generate DMA requests. The fifth timer does not have external pin connections and may be used for internal timing operations.
  • One SCTimer/PWM with eight input and ten output functions (including capture and match). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events, and 16 states.
  • 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. A timer in the RTC can be used for wake-up from all low power modes including deep power-down, with 1 ms resolution.
  • Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.
  • Windowed Watchdog Timer (WWDT).
  • Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose use.

Security features

  • AES-256 encryption/decryption engine with keys stored in polyfuse OTP. Random number generator can be used to create keys with DMA support.*
  • Secure Hash Algorithm (SHA1/SHA2) module supports secure boot with dedicated DMA controller.*
  • PUF block that can generate, store, and reconstruct key sizes from 64 to 4096 bits.*

Clock generation

  • 12 MHz internal Free Running Oscillator (FRO). This oscillator provides a selectable 48 MHz or 96 MHz output, and a 12 MHz output (divided down from the selected higher frequency) that can be used as a system clock. The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range.
  • External clock input for clock frequencies of up to 25 MHz.
  • Crystal oscillator with an operating range of 1 MHz to 25 MHz.
  • Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz.
  • 32.768 kHz low-power RTC oscillator.
  • System PLL allows CPU operation up to the maximum CPU rate and can run from the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHz RTC oscillator.
  • Two additional PLLs for USB clock and audio subsystem.
  • Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.
  • Clock output function with divider.
  • Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal.

Power control

  • Programmable PMU (Power Management Unit) to minimize power consumption and to match requirements at different performance levels.
  • Reduced power modes: sleep, deep-sleep, and deep power-down.
  • Wake-up from deep-sleep modes due to activity on the USART, SPI, and I2C peripherals when operating as followers
  • Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be used to wake up the device from low power modes.
  • Power-On Reset (POR).
  • Brown-Out-Detect (BOD) with separate thresholds for interrupt and forced reset.

Additional information

  • DMIC subsystem including a dual-channel PDM microphone interface, flexible decimators, 16 entry FIFOs, optional DC locking, hardware voice activity detection, and the option to stream the processed output data to I2S.
  • Single power supply 1.71 V to 3.6 V.
  • Power-On Reset (POR).
  • Brown-Out-Detect (BOD) with separate thresholds for interrupt and forced reset.
  • JTAG boundary scan supported.
  • 128-bit unique device serial number for identification.
  • Operating temperature range -40 °C to +105 °C.
  • Available in TFBGA180, TFBGA100, LQFP208, and LQFP100 packages.
  • Supported by MCUXpresso SDK, IDE and Config Tools

Part numbers include: LPC54005JBD100, LPC54005JET100, LPC54016JBD100, LPC54016JBD208, LPC54016JET180, LPC54018J2MET180, LPC54018J4MET180, LPC54018JBD208, LPC54018JET180, LPC54S005JBD100, LPC54S005JET100, LPC54S016JBD100, LPC54S016JBD208, LPC54S016JET100, LPC54S016JET180, LPC54S018J2MET180, LPC54S018J4MET180, LPC54S018JBD208, LPC54S018JET180.

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