Layerscape® 1012A Low Power Processor

LS1012A

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The LS1012A processor, optimized for battery-backed or USB-powered, space-constrained networking and IoT applications, integrates a single Arm® Cortex®-A53 core running up to 1GHz with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance in an ultra-small size envelope at 1W typical power dissipation. The LS1012A incorporates the same Trust Architecture and software compatibility of higher-tier LS family devices, enabling scalable, secure applications that leverage a common 64-bit software platform.

Layerscape processors are part of NXP's EdgeVerse™ edge computing platform.

Product Details

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Block Diagram

LS1012A Block Diagram

LS1012A Block Diagram
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Features

Core Complex

  • Single 600 MHz or 1GHz Arm® Cortex®-A53 core
  • 32 KB-I and 32 KB-D ECC protected cache
  • 256 KB L2 ECC protected cache
  • Over 4000 Coremarks performance

Networking Elements

  • Three-lane SerDes up to 6 GHz multiplexed across controllers supporting
    • One PCI Express® Gen 2 interface
    • One SATA 3.0 Interface
    • Two 1Gb or 2.5Gb Ethernet Controllers

Accelerators and Memory Controllers

  • Packet Forwarding Engine
  • Integrated security engine (SEC)
  • 16-bit DDR3L Memory Controller
  • QuadSPI Flash Memory Interface

Basic Peripherals and Interconnect

  • 1x USB 3.0 + PHY
  • 1x USB 2.0 + ULPI
  • 1x SPI, 2x I2C
  • 2x SD3.0 / SDIO / eMMC
  • 2x UART
  • 5x I2S

Additional Features

  • QorIQ® Trust Architecture
  • Arm TrustZone
  • 9.6 x 9.6mm L-BGA package

Part numbers include: LS1012ASE7EKA, LS1012ASE7EKB, LS1012ASE7HKA, LS1012ASE7HKB, LS1012ASE7KKB, LS1012ASN7EKA, LS1012ASN7EKB, LS1012ASN7HKA, LS1012ASN7HKB, LS1012ASN7KKB, LS1012AXE7EKA, LS1012AXE7EKB, LS1012AXE7HKA, LS1012AXE7HKB, LS1012AXE7KKB, LS1012AXN7EKA, LS1012AXN7EKB, LS1012AXN7HKA, LS1012AXN7HKB, LS1012AXN7KKB.

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