i.MX RT500 Crossover MCU with Arm® Cortex®-M33, DSP and GPU Cores

i.MX-RT500

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i.MX RT500 Crossover MCUs are dual-core devices featuring an Arm® Cortex®-M33 and Cadence® Xtensa® Fusion F1 DSP, designed for low power wearable and consumer IoT applications.

The i.MX RT500 CM33 operates at up to 275 MHz and includes two coprocessors providing enhanced performance. The Fusion DSP operates at up to 275 MHz. The family offers a rich set of peripherals, embedded security and very low power consumption. The device has up to 5 MB SRAM and two FlexSPIs each with 32 KB cache.

The i.MX RT500 family is supported by the MCUXpresso ecosystem, which includes an SDK, a choice of IDEs and secure provisioning and configuration tools to enable rapid development.

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Block Diagram

i.MX RT500 Crossover MCU

i.MX RT500 Crossover MCU
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Features

Cortex-M33 Core Running at a Frequency of up to 275 MHz

  • Arm TrustZone® for asset protection
  • Cortex-M33 built-in memory protection unit (MPU) supporting eight regions
  • Two coprocessors for the Cortex-M33
    • PowerQuad hardware accelerator for (fixed and floating point unit) DSP functions
    • CASPER crypto coprocessor to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms

Highly Optimized Cadence® Tensilica® Fusion F1 DSP Processor Core Running at Frequencies of up to 275 MHz

  • Hardware floating point unit; single-precision IEEE floating point MAC per cycle

Software and Tools

  • MCUXpresso ecosystem support
    • Selection of IDE choices
    • Pin, clock, peripheral, security and memory Config tools
    • Security programming and provisioning tools
    • Software Development Kit
  • Zephyr RTOS support

On-Chip Memory

  • Up to 5 MB of system SRAM accessible by both CPUs and all DMA engines
  • 2 x 32 kB FlexSPI cache

Graphics

  • 2D GPU with vector graphics acceleration
  • CSI 8/10/16-bit parallel (FlexIO)
  • LCD 8/10/16/18/24-bit parallel (FlexIO)
  • LCD Interface + MIPI DSI

Digital Peripherals

  • Two DMA engines, each with 32 channels
  • Quad/Octal SPI Flash with a dynamic description
  • Two SD/eMMC memory card interfaces—one supporting eMMC 5.0 with HS400/DDR operation
  • USB high-speed host/device controller with on-chip PHY
  • Up to 12 configurable universal serial interface modules (FlexComm interfaces) configurable as SPI/I2C/I2S/UART
  • One high-speed SPI interface supporting 50 MHz operation
  • Two I3C bus interfaces
  • A digital microphone interface supporting up to 8 channels

Features

Cortex-M33 Core Running at a Frequency of up to 275 MHz

  • Arm TrustZone® for asset protection
  • Cortex-M33 built-in memory protection unit (MPU) supporting eight regions
  • Two coprocessors for the Cortex-M33
    • PowerQuad hardware accelerator for (fixed and floating point unit) DSP functions
    • CASPER crypto coprocessor to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms

Highly Optimized Cadence® Tensilica® Fusion F1 DSP Processor Core Running at Frequencies of up to 275 MHz

  • Hardware floating point unit; single-precision IEEE floating point MAC per cycle

Software and Tools

  • MCUXpresso ecosystem support
    • Selection of IDE choices
    • Pin, clock, peripheral, security and memory Config tools
    • Security programming and provisioning tools
    • Software Development Kit
  • Zephyr RTOS support

On-Chip Memory

  • Up to 5 MB of system SRAM accessible by both CPUs and all DMA engines
  • 2 x 32 kB FlexSPI cache

Graphics

  • 2D GPU with vector graphics acceleration
  • CSI 8/10/16-bit parallel (FlexIO)
  • LCD 8/10/16/18/24-bit parallel (FlexIO)
  • LCD Interface + MIPI DSI

Digital Peripherals

  • Two DMA engines, each with 32 channels
  • Quad/Octal SPI Flash with a dynamic description
  • Two SD/eMMC memory card interfaces—one supporting eMMC 5.0 with HS400/DDR operation
  • USB high-speed host/device controller with on-chip PHY
  • Up to 12 configurable universal serial interface modules (FlexComm interfaces) configurable as SPI/I2C/I2S/UART
  • One high-speed SPI interface supporting 50 MHz operation
  • Two I3C bus interfaces
  • A digital microphone interface supporting up to 8 channels

Security Features

  • Secure isolation: secure execution environment through Arm® TrustZone® technology for ARMv8-M, symmetric key isolation through hardware engines
  • Secure boot supports implemented in boot ROM, providing immutable root of trust
  • Secure storage: physically unclonable function (PUF) based key store, on-the-fly AES decryption (OTFAD) of off-chip flash for code storage
  • Secure debug: certificate-based debug authentication mechanism
  • Secure update supports firmware update with authenticity (RSA signed) and confidentiality (AES-CTR encrypted) protection
  • Hardware cryptography accelerators:
    • Symmetric cryptography (AES) with 256-bit key strength
    • Asymmetric cryptography acceleration
    • TRNG with 256-bit entropy
    • Hash engine with SHA-256 and SHA-1
  • Secure identity: 128-bit universal unique identifier (UUID) and 256-bit compound device identifier (CDI)
  • A member of the EdgeLock Assurance program, providing on-chip security capabilities.

Part numbers include: MIMXRT533SFAWC, MIMXRT533SFFOC, MIMXRT555SFAWC, MIMXRT555SFFOC, MIMXRT595SFAWC, MIMXRT595SFFOC.

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